Electrostatic discharge into a semiconductor integrated circuit (IC) can cause failure of the components unless they are properly ESD protected. This is normally achieved by making special components and circuits which reside in the input/output (TO) regions of the circuit. This invention describes MOSFETs which are suitable for use within input or output protection circuits. At least some embodiments of such MOSFETs can be manufactured using mainstream CMOS processing techniques so that they can exist alongside many other useful components on/in a single integrated circuit.
ESD pulses tend to have a very short duration and can be discharged into an IC through its electrical terminals. Hence these input/output (TO) terminals should be tolerant to withstand very fast transient, high voltage spikes. This is normally accomplished using protection circuits composed of diodes, resistors and MOSFETs. For example, and without limitation, NMOS and PMOS devices may be used.
One IO protection scheme, see FIG. 1, comprises the addition of diodes 106, 108 connected to the power rails 102, 104. In FIG. 1, a bond pad 110 is shown. This is connected to other circuits 112 via line 111. The bond pad 110 allows external connections to be made to circuits 112 (the structure of circuits 112 is normally too small for external connections to be made directly to circuits 112), via terminals on the bond pad. Accordingly, the terminals of the bond pad 110 provide the IO functionality of the chip 100. Whilst only one line 111 is shown in FIG. 1, a separate line is provided for each terminal of the bond pad 110, and a set of diodes such as diodes 106, 108 is normally provided for each line. The terminals of the bond pad 110 are normally exposed. This is why they constitute an ESD risk (the bond pad 110 is effectively a gateway for ESD to reach other circuits 112 on the chip). The description will proceed as if there was only one line and one terminal on the bond pad 110, but it will be understood that normally there are several.
The diodes 106, 108 are reverse biased when the chip 100 is powered and conduct minimal current in this operational mode. If the voltage on the IO exceeds (due to ESD) the power supply voltage Vdd, the upper diode 108 will forward bias to the Vdd rail 104. Conversely, a negative voltage to the IO will forward bias the lower diode 106 to the Gnd rail 102. Hence the voltage level at the pad terminal (i.e. at node 114) is “clamped” within a voltage range which can be tolerated by the rest of the circuit, i.e. between 0V and Vdd.
If the Vdd 104 is unconnected, an ESD pulse can reverse bias the lower IO diode 106 connected to the ground rail, until it conducts due to reverse bias breakdown. A similar situation can occur for reverse polarity ESD pulses applied to the upper Vdd connected diode 108 if the ground 102 is disconnected. When designing ESD protection schemes one should therefore give consideration to the reverse bias breakdown properties of these IO connected diodes.
Input protection diodes may be made e.g. using MOSFETs, for example large MOSFETs, where the gate, source and body are connected together for the power rail (Vdd or ground) connected side of the diode, and the drain node forms the side which is connected to the pad, at node 114.
In a typical configuration a NMOS transistor would be used where lower diode 106 is shown in FIG. 1, and a PMOS transistor would be used where upper diode 108 is shown. The drains of both transistors would be connected to node 114 (pad). The gate, source and body of the NMOS transistor 106 would be connected together to ground 102, and the gate, source and body of the PMOS transistor 108 would be connected together to Vdd 104.
For NMOS devices this is commonly known as ggNMOS connection configuration (grounded gate NMOS) because of the connection of the gate of the NMOS to the ground rail. As described above, the wiring for the PMOS device is equivalent (but opposite) for the power supply connection, Vdd rail 104.
For outputs a similar arrangement can be used. In that case the IO buffer transistors are usually large NMOS and PMOS devices which have intrinsic reverse biased diodes on the drain nodes relative to the source, body and power rails. The gate connections of the output drivers are connected to the internal output signal wiring of the IC.
Furthermore, additional protection diodes can be added between the Vdd and ground rail in order to protect the IC from ESD surges between the power connections. Alternatively a power supply clamp circuit 116 may be employed to limit the voltage surge between power rails in the event of an ESD surge between Vdd and ground. Diodes and clamps can also be used in more complicated ways when multiple power supplies are used on the IC. High voltage ICs are also made where the circuit controls the switching of high voltages which are not available as power supply connections to the component. These operation requirements further complicate the design of suitable ESD protection schemes compared to the simple example of FIG. 1. Nevertheless, FIG. 1 illustrates the basic idea of how an ESD protection circuit can be made on an IC.
For simplicity this description will focus next on the NMOS component, which is representative of MOSFET behavior in general when it is used within ESD protection circuits.
ESD pulses can be discharged into an NMOS protection device by a combination of reverse bias breakdown of the drain to body diode and also by breakdown of the parasitic bipolar NPN junctions between source, body and drain. The challenge of ESD protection is to ensure that the breakdown current flowing into the MOSFET is, as much as possible, uniformly spread over the whole device—or at least more uniformly spread than it would be without the ESD protection. Localised current flows can lead to self heating damage of the component in “hot spots”. Also, the resistance of the device once it conducts should be low so that resistive self heating is minimized, or at least reduced. Also, the current from the ESD pulse can be discharged with minimal voltage rise within the IC. High voltages can also be damaging to the IC, e.g. causing destructive breakdown of thin insulating layers, e.g. the gate dielectric. ESD protection devices tend to have a large physical area compared to many other components. They are large to spread out the energy of the ESD discharge and also to minimise their series resistance, which is inversely proportional to their size. A typical configuration for a protection device is an NMOS made from a number of long parallel gate fingers with alternate connections to the drain, source and body regions. Small distances between drain and source and drain and body are therefore maintained.
However, in order to promote a more uniform current flow in an ESD protection structure, small resistive regions can be formed which are associated with the drain side of the MOSFET. These are often termed “ballast resistors” and may be constructed in a number of ways. Referring to FIG. 2, one common technique is to make the MOSFET with a slightly longer region of drain diffusion resistance 20 between the drain side of the channel and the drain ohmic metal connection. However, a problem arises in this technique: The process of forming the device uses silicide (e.g. the silicide 15 of the body contact). There is therefore the risk that—without additional precautions—silicide could also form in other areas, for example on drain diffusion resistance 20, which would then be shorted, given that an overlying metallic silicide would have a low series resistance. Accordingly, a thin stripe of silicide blocking material 7 is used. This may be an insulating dielectric layer. By overlapping the gate 9 on the drain side with silicide blocking material 7 and extending this towards the drain connection the risk of silicidation of the diffusion region 20 adjacent to the MOSFET channel is avoided. The diffusion region 20 (or drain diffusion) then acts as the ballast resistor.
On the source side the diffusion 14 can be fully silicided. The gate 9, where it is only partially overlapped by silicide blocking material 7, can also become partly silicided to keep its resistance low. Alternatively the gate 9 could be overlapped completely by the silicide block 7, if it would otherwise become too narrow to form silicide upon it in a self-aligned silicide (salicide) process. Other process variants include separately silicided gates or using metallic gates where the presence of a silicide block layer on the gate is less problematic.
A cross-section of a typical, conventional ESD protection NMOS structure as described above can be seen in FIG. 2.
Several additional techniques have been used to improve modern ESD MOSFETs. One method commonly used is to modify the drain junction diffusion so that it is deeper and the doping profile is a more graded diffusion region (not an abrupt doping transition), such as diffused region 19—see FIG. 3. The junction depth is indicated by “xj” in FIG. 3. This tends to modify the behavior of the junction breakdown and forces ESD current flow deeper into the semiconductor, where it causes less damage to the MOSFET. Also, the rounding and more diffused grading of the junction edge lowers the electric field within the transistor, which is beneficial to mitigate any ESD surge damage.